PIC16F87T-E/ML【PDF 152/200 页】IC MCU FLASH 4KX14 EEPROM 28QFN

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8008H–AVR–04/11

ATtiny48/88

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in Table 6-5 on page 33.

If the low level on the interrupt pin is removed before the device has woken up then program

execution will not be diverted to the interrupt service routine but continue from the instruction fol-

lowing the SLEEP command.

9.3

Register Description

9.3.1

EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bits 7:4 – Res: Reserved Bits

These bits are reserved and will always read zero.

Bits 3:2 – ISC1[1:0]: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the

interrupt are defined in Table 9-2. The value on the INT1 pin is sampled before detecting edges.

If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate

an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is

selected, the low level must be held until the completion of the currently executing instruction to

generate an interrupt.

Bits 1:0 – ISC0[1:0]: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 9-3. The value on the INT0 pin is sampled before detecting edges.

If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate

an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is

Bit

654

(0x69)

–

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

Table 9-2.

Interrupt 1 Sense Control

ISC11

ISC10

Description

The low level of INT1 generates an interrupt request.

Any logical change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

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